1. Field of the Invention
The present invention relates to a solid-state imaging device, a method for producing the same, and a mobile electronic device including the same. More specifically, the present invention relates to a solid-state imaging device used for video cameras, digital cameras, and camera-equipped cellular phones such as, for example, a threshold voltage modulation system MOS image sensor; a method for producing the same; a mobile electronic device including the same.
2. Description of the Related Art
Semiconductor image sensors such as, for example, CCD-type image sensors and MOS image sensors are easily and effectively mass-produced and are conventionally used as an image input device in mobile electronic devices including video cameras, digital cameras and camera-equipped cellular phones. Since such mobile electronic devices are operated by batteries, it is important to reduce the driving voltage and power consumption. It is also important to reduce production costs and module size. As compared to CCD image sensors, MOS image sensors consume less power and are produced at lower cost using a conventional CMOS process. The MOS image sensors can also be reduced in module size by forming sensor devices and peripherals on one chip. For these reasons, the MOS image sensors now attract attention.
As examples of such MOS image sensors, Japanese Laid-Open Publications Nos. 11-195778, 2001-160620 and 2001-177085 disclose a threshold voltage modulation system MOS image sensor as shown in FIGS. 5 and 6.
FIG. 5 is a plan view showing an exemplary layout of a unit pixel section 210 in a conventional MOS image sensor as disclosed in the above-mentioned publications. FIG. 6 is a cross-sectional view of the unit pixel section 210 taken along line A–A′ in FIG. 5. Although not shown, the MOS image sensor includes a plurality of unit pixel sections 210 in a matrix, i.e., in rows and columns.
As shown in FIGS. 5 and 6, the unit pixel section 210 includes a light receiving diode 211 for receiving light and a signal detecting MOS transistor 212 for detecting a signal representing an amount of light received by the light receiving diode 211 and outputting the signal. The light receiving diode 211 is provided adjacent to the MOS transistor 212. As disclosed in, for example, Japanese Laid-Open Publication No. 2002-50753, the unit pixel sections 210 adjacent to each other in a row direction are separated from each other by pixel separation electrodes 213a and 213b. The pixel separation electrodes 213a and 213b are formed in the step of forming a gate electrode.
As shown in FIG. 6, reference numeral 214 refers to a p-type silicon substrate or a p-type epitaxially grown semiconductor layer provided on the silicon substrate (hereinafter, both referred to also ass a “p-type layer 214”). In the p-type layer 214, an n-type layer 215 is provided in both an area of the light receiving diode 211 and an area of the MOS translator 212. On the n-type layer 215, a p-type well region 216a is provided in the light receiving diode 211, and a p-type well region 216b is provided in the MOS transistor 212. The p-type well region 216a and the p-type well region 216b are formed by different production steps.
The p-type well region 216a in the light receiving diode 211 acts as a light receiving region for generating charges corresponding to an amount of light incident thereon. In the p-type well region 216b, a carrier pocket region 217 is provided for accumulating the charges generated by the p-type well region 216a. The MOS transistor 212 includes a gate region capable of changing the threshold voltage of a channel region based on the potential, in proportion to the charges accumulated in the carrier pocket region 217. The gate region is formed of the p-type well region 216b. In the light receiving diode 211, an n-type layer 218 is provided below the n-type layer 218. In the MOS transistor 212, a p-type buried layer 219 is provided below the n-type layer 215.
In the light receiving diode 211, an n-type impurity region 220 is provided on a surface of the p-type well region 216a. Thus, a burying structure for burying the charges generated in correspondence with the amount of incident light is provided.
In the MOS transistor 212, an annular gate electrode 222 in provided above the p-type well region 216b with a gate insulating layer 221 interposed therebetween. An n-type source region 223 is provided in a surface region of the p-type well region 216b, below an area surrounded by the gate electrode 222.
An n-type drain region 224 is provided so as to surround the p-type well regions 216a and 216b. The source region 223 is connected to a source electrode 226 via a contact hole 226a. The drain region 224 is connected to a drain electrode 227 via a contact hole 227a. The gate electrode 222 is connected to a gate line (not shown) via a contact hole 228a. 
An n-type well separation region 229 is provided below the drain region 224, and the drain region 224 is in contact with the n-type layer 215 via the well separation region 229. An n-type channel dope layer 230 is provided below the gate electrode 222 with the gate insulating layer 221 interposed therebetween. The channel dope layer 230 forms the channel region. The carrier pocket region 217 is provided at a position which is below the channel region, in the p-type well region 216b and in the vicinity of the source region 223. In this specification, the carrier pocket region is also referred to as a charge accumulation region. The charge accumulation region acts as a hole pocket region for accumulating holes and is also referred to as a “hole pocket region”. In the hole pocket region 217, holes generated by light irradiation by the light receiving diode 211 are accumulated. A hole is an example of an optical signal carrier. The threshold voltage of the MOS transistor 212 changes in accordance with the amount of the optical signal carriers accumulated in the hole pocket region 217.
Hereinafter, an operation of the MOS image sensor having the above-described structure will be briefly described.
In the MOS image sensor, a series of operations, i.e., an initial operation (a reset operation) to a charge accumulation operation to a signal read operation are performed repeatedly.
In a period of the initial operation, the gate electrode 222, the source electrode 226 and the drain electrode 227 are supplied with a positive high voltage, and holes (optical signal carriers) remaining in the hole pocket region 217 are discharged toward the p-type layer 214.
Next, in a period of the charge accumulation operation, holes newly generated by irradiation of the light receiving diode 211 with light are accumulated in the hole pocket region 217.
In a period of the signal read operation, a signal representing an amount of holes accumulated in the hole pocket region 217 in output from the source region 223.
A method for producing the MOS image censor will be described with reference to FIGS. 7A through 7H.
FIGS. 7A through 7H are cross-sectional views illustrating a production method of the MOS image sensor shown in FIGS. 5 and 6. The cross-sectional views ale along line A–A′ in FIG. 5.
As shown in FIG. 7A, a mask pattern layer 231 having an opening at an area where the light receiving diode 211 is to be formed is used to implant n-type impurities into the p-type layer 214, thereby forming the n-type layer 218 in the area where the light receiving diode 211 is to be formed. The p-type well region 216a is also formed so as not to contact the n-type layer 210.
Next, as shown in FIG. 7B, the mask pattern layer 231 is removed and n-type impurities are implanted, thereby forming the n-type layer 215 in the entire planar area at a level in the p-type layer 214. The n-type layer 215 is provided between and in contact with the n-type layer 218 and the p-type well region 216a. 
As shown in FIG. 7C, a mask pattern layer 232 having an opening at an area where the MOS transistor 212 is to be formed is used to implant p-type impurities into an area of the p-type layer 214 below the n-type layer 215. The p-type buried layer 219 has a role of fixing the potential of the p-type buried layer 219 to the potential of the p-type layer 214. By this implantation, the p-type buried layer 219 having a higher impurity concentration than that of the n-type layer 215 is formed. The p-type buried layer 219 is adjacent to the n-type layer 218. The mask pattern layer 232 is again used to implant p-type impurities into form the p-type well region 216b on the n-type layer 215. The p-type well region 216b is formed to be aligned with the p-type well region 216a. 
As shown in FIG. 7D, a mask pattern layer 233 having an opening which is sufficiently larger than the light receiving diode 211 and also the MOS transistor 212 is used to implant n-type impurities, thereby forming the n-type channel dope layer 230 on a surface of the p-type well region 216a and the p-type well region 216b. The n-type channel dope layer 230 acts as a channel region.
As shown in FIG. 7E, a mask pattern layer 234 having an opening in an area corresponding to an area outside the p-type well region 216a and the p-type well region 216b is used to implant n-type impurities, thereby forming the well separation region 229, which surrounds the p-type well region 216a and the p-type well region 216b. 
As shown in FIG. 7F, a mask pattern layer 235 having an opening in an area where the hole pocket region 217 is to be formed is used to implant p-type impurities into the p-type well region 216b. Thus, the hole pocket region 217 having a higher impurity concentration than that of the p-type well region 216b is formed in an annular shape.
After the mask pattern layer 235 is removed, the surface of the resultant laminate is thermally oxidized, thereby forming the gate insulating layer 221 as depicted in FIG. 7G.
As shown in FIG. 7G, the annular gate electrode 222 is formed on the gate insulating layer 221 so as to cover the hole pocket region 217.
As shown in FIG. 7H, the source region 223 is formed in an area surrounded by, and in the vicinity of, the annular hole pocket region 217. The area in which the source region 223 is formed is directly below the area surrounded by the gate electrode 222. The drain region 224 is formed in an area corresponding to an area surrounding the gate electrode 222 and the light receiving diode 211. In addition, n-type impurities are implanted into the n-type channel dope layer 230 to form the n-type impurity region 220.
In this manner, the MOS image sensor including the light receiving diode 211 and the MOS transistor 212 is produced.
The above-described MOS image sensor has the following problems.
The p-type well region 216a included in the light receiving diode 211 is formed using the mask pattern 231, and the p-type well region 216b included in the MOS transistor 212 in formed using the mask pattern 232. Due to the misalignment during the photolithography step, the manner in which the p-type well region 216a and the p-type well region 216b are positioned is variable. The impurity concentration distribution at the interface between the p-type well regions 216a and 216bis unstable. This causes serious variance in the characteristics of charge transfer, by which the optical signal carriers generated in the light receiving diode 211 are transferred to the carrier pocket region 217.
In the NOS image sensor described in Japanese Laid-Open Publication No. 2001-177085, the interface between the p-type well regions 216a and 216b has a higher impurity concentration than that of the p-type well region 216a and 216b. It is explained that this promotes the transfer of the optical signal carriers generated in the p-type well region 216a to the p-type well region 216b, which results in easier transfer of the optical signal carriers to the hole pocket region 217. It is necessary to ensure that the p-type well regions 216a and 216b are positioned uniformly. With the above-described conventional method for producing the MOS image sensor, it is difficult to mass-produce the MOS image sensors in such a uniform state. The present inventors tried to produce the MOS image sensor described in Japanese Laid-Open Publication No. 2001-177085. Rather than the effect of promoting the transfer of the optical signal carriers as described in the publication, the following disadvantages were more conspicuously presented: (i) the optical signal carriers remained at an interface between the p-type well regions 216a and 216b, generating an afterimage, and (ii) the p-type well regions 216a and 216b are substantially separated due to the misalignment, generating a portion having a lower carrier concentration than that of the p-type well regions 216a and 216b, and the optical signal carriers remain in the light receiving diode 211, destabilizing the sensitivity.
There is also a problem of misalignment between the mask pattern layer 231 for determining the position of the light receiving diode 211 and the mask pattern layer 234 for determining the position of the n-type well separation region 229 between adjacent unit pixel sections 210. Exemplary problems are (i) sensitivity variance caused by a change in the planar area of the light receiving diode 211, and (ii) variance in the amount of dark current generated due to the variance in the semiconductor junction profile between the light receiving diode 211 and the n-type well separation region 229.